The present invention relates to semiconductor devices and, more particularly to memory devices and methods of manufacturing memory devices.
Semiconductor memory devices may be divided into volatile memory devices that may have relatively fast response speed and nonvolatile memory devices that may have a slower response speed relative to the volatile memory devices. The volatile memory devices may include dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. The volatile memory device may lose data stored therein when a power supply is removed and/or turned off. The non-volatile memory devices may include erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices and/or flash memory devices. The nonvolatile memory device may maintain stored data therein even when a power supply is removed and/or turned off.
The flash memory devices may be classified into floating gate type memory devices and/or charge trapping type memory devices. A floating gate type memory device may be programmed and erased by storing and/or removing free charges into and/or from a floating gate thereof. A charge trapping type memory device may be programmed and/or erased by storing electrons and/or holes into a charge trapping layer thereof.
When a dielectric layer is formed on a floating gate of the charge trapping type memory device, the dielectric layer may have a thin thickness to achieve a desirable coupling ratio. However, when the dielectric layer has a very thin thickness, a leakage current may increase and thus may deteriorate electrical characteristics of the non-volatile memory device. Additionally, when a polysilicon layer and/or a polysilicon layer doped with impurities is used as the floating gate of tile charge trapping type memory device, data retention characteristics of the memory device may deteriorate over time such that the memory device may have a poor reliability. For example, when an N type polysilicon layer serves as the floating gate, the memory device may have bad data retention characteristics. Although a P type polysilicon layer having a work function larger than that of the N type polysilicon layer may serve as the floating gate, a threshold voltage in an erasing operation of the memory device may be considerably increased.